ACER Computer GmbH                                     Kornkamp 4
                                                       D-22926 Ahrensburg
                                                       GERMANY
                                                       Tel: 04102 / 488-0
                                                       Fax: 04102 / 488-169

ACER PCI-BIOS  Version 2.1


POSTcode       TEST-DESCRIPTION

  04           Determines if the current booting procedure is from cold
               boot (press reset button or turn the system on), from 
               warm boot (Ctrl-Alt-Del), or from exiting BIOS setup.

               Note:  At the beginning of POST, port 64 bit 2 (8042 
                      system flag) is read to determine whether this POST 
                      is caused by a cold or warm boot. If it is a cold 
                      boot, a complete POST is performed. If it is a warm 
                      boot, the chip initialisation and memory test is 
                      eliminated from the POST routine.

  08           Disabless PIE (periodical interrupt enable), AIE (alarm 
               interrupt enable) and UIE (update-ended interrupt enable).

               Note: These interrupts are disabled to avaid interrupting 
                     the POSt routine.

  10           DMA controller(8237) test and initialization.

  14           System timer (8237) test and initialization.

  18           Memory refresh test, refresh occurance verification (IRQ0).

  1C           Verifies CMOS shutdown byte, battery and checksum.

               Note: Several parts of the POST routine require the system
                     to be in protected mode. When running in protected 
                     mode, the processor is reset, therefor e POST is 
                     re-entered. In order to prevent re-initialization of 
                     the system, POST reads the shutdown code stored in 
                     location 0Fh in CMOS RAM. Then it jumps around the 
                     initialization procedure to the appropriate entry 
                     point. The CMOS shutdown byte verification assures 
                     that CMOS 0Fh area is fine to execute POST properly.

               Initializes default CMOS setting.
               Initializes RTC (Real-Time Clock) time base.

               Note: The RTC has an embedded oscillator that generates 
                     32.768 kHz frequency. To initialize RTC time base, 
                     turn on this oscillator and set a divisor to 32768
                     so that RTC can count time correctly.

  20           Test keyboard controller (8041/8042).
               Determine keyboard type.

  24           Testing and initializing PIC (8259).
               Initializes system interrupt.

  2C           Test 128 kB base memory.

               Note: The 128K base memory area is tested for POST 
                     execution. The remaining memory area is tested
                     later.

  3C           Sets interrupt service for POST.

  4C           Checks CPU brand, ID and frequency.

  50           Initialize video display.

               Note: If the system has any display card, it should be 
                     initialized here via its I/O Rom or the corresponding 
                     initialization program.

  58           Display Acer (or OEM) logo (if necessary).
               Display Acer copyright message (if necessary).
               Display BIOS serial number.
     
  5C           Memory test (axcept the 128K base memory).

  60           Initializes SRAM cache capacity.
               Enables the cache function.
     
  62           Configure system resource.
               Initialize PCI device.
     
  64           Tests keyboard interface.

               Note: The keyboard LED should flash once.

  68           Enables UIE, then checks RTC update cycle.

               Note: The RTC executes an update cycle per second. When the
                     UIE is set, an interrrupt (IRQ8) occurs after every 
                     update cycle and indicates  that over 999 ms are 
                     available to read valid time and date information.

  6C           Tests FDD parameter table setup.

               Note: The FDD LED should flash  once and its head should be positioned.

  70           Initializes parallel port.

  74           Initializes serial port(s).

  84           Initializes keyboard.
     
  88           Sets HDD type and features (i.e. transfer speed, mode,...).
               Tests HDD controller.

  94           Initialize I/O ROM.

               Note: I/O ROM is an optional extension of the BIOS located on an 
                     installed add-on card as a part of the I/O subsystem. POST
                     detects I/O ROMs and gives them oportunity to initialize 
                     themselves and their hardware environment.
     
  96           Initializes PCI I/O ROM.

  A0           Sets time and date.

  B0           Power-on password checking.
               Display configuration mode table.
               Booting.
     
