ACER Computer GmbH                                     Kornkamp 4
                                                       D-22926 Ahrensburg
                                                       GERMANY
                                                       Tel: 04102 / 488-0
                                                       Fax: 04102 / 488-169

ACER PCI-BIOS  Version 3.0 (PCI/EISA)


POSTcode       TEST-DESCRIPTION

  03           Determines BSP.

  04           Check CPU ID.
               Dispatch shutdown path.
               Determines if the current booting procedure is from cold
               boot (press reset button or turn the system on), from 
               warm boot, or from exiting BIOS setup.

               Note:  At the beginning of POST, port 64 bit 2 (8042 
                      system flag) is read to determine whether this POST 
                      is caused by a cold or warm boot. If it is a cold 
                      boot, a complete POST is performed. If it is a warm 
                      boot, the chip initialisation and memory test is 
                      eliminated from the POST routine.

  08           Resets video frame buffer.
               Resets PIE (periodical interrupt enable), AIE (alarm 
               interrupt enable) and UIE (update-ended interrupt enable).

               Note: These interrupts are disabled in order to avaid any 
                     mis-action happened during the POSt routine.

  09           Initializes chipset settings according to CPUs.

  10           Tests and initializes DMA (8237).

  14           Tests and initializes system timer (8237).

  18           Test DRAM refresh cycle, sets default SS:SP=0:400.

  1C           Verifies CMOS shutdown byte, battery and checksum.

               Note: Several parts of the POST routine require the system
                     to be in protected mode. When running in protected 
                     mode, the processor is reset, therefor e POST is 
                     re-entered. In order to prevent re-initialization of 
                     the system, POST reads the shutdown code stored in 
                     location 0Fh in CMOS RAM. Then it jumps around the 
                     initialization procedure to the appropriate entry 
                     point. The CMOS shutdown byte verification assures 
                     that CMOS 0Fh area is fine to execute POST properly.

               Initializes default CMOS setting if CMOS is bad.
               Initializes RTC (Real-Time Clock) time base.

               Note: The RTC has an embedded oscillator that generates 
                     32.768 kHz frequency. To initialize RTC time base, 
                     turn on this oscillator and set a divisor to 32768
                     so that RTC can count time correctly.
   
  1E           Determines DRAM type.

  1F           Initializes RDM (Phase I)

  20           Test keyboard controller (8041/8042).
               Determine keyboard type.
               Write default command byte upon keyboard type.

  21           Initializes PCEB and ESC

  22           Initializes EISA slots.

  24           Testing and initializing PIC (8259).

  25           BIOS bootable setting.

  2C           128K base memory testing. Set default SS:SP=0:400.

               Note: The 128K base memory area is tested for POST 
                     execution. The remaining memory area is tested
                     later.

  30           System shadow RAM.

  34           DRAM sizing.

  35           Scans the PCI devices and initialize PCI Slots

  36           Loads Pentium Pro CPU update code.

  3C           Initializes interrupt vectors.

  40           Initializes PCI (1.), sets I/O range to OPB

  41           Initializes PCI (2.), memory

  42           Initializes PCI (3.), pre-memory

  44           Initializes PCI (4.).

  45           Initializes PCI (5.). 

  4C           Tests system board requests.

  4E           Scans PnP devices.

  4F           Configures PNP devices.

  50           Initialize video display.

  51           Copies ROM code to RAM.

  58           Set POST screen mode (graphic or text).
               Display Acer (or OEM) logo (if necessary).
               Display Acer copyright message (if necessary).
               Display BIOS serial number.
     
  59           Hooks INT 1Ch for quiet boot.

  5A           Initializes SMRAM, SMI handler.

  5C           Test memory.

  5E           Loads Pentium Pro CPU update code.

  60           Sizes external cache. 
               Tests external cache (SRAM and controller).
               Enables internal cache (if necessary).
               Enables exeternal cache (if necessary).
          
  64           Resets keyboard device.
               Checks keyboard status.

  6C           Tests FDD parameter table setup.

               Note: The FDD LED should flash  once and its head should be positioned.

  70           Tests parallel port.

  74           Tests serial port.

  75           Initializes RDM (Phase II).

  78           Tests math coprocessor.

  7C           Resets pointing device.
               Checks pointing device.
     
  80           Sets security status.

  82           Copies Setup code from ROM to RAM.

  84           Initialize keyboard.
               Set keyboard LEDs upon setup requests.     
               Enable keyboard device.
     
  88           HDD test and parameter table setup.

  89           Tests CPU internal frequency.

  90           Display POST status (if necessary).
               Changes POST mode to default text mode.

  93           Rehooks INT 1Ch for quiet boot.

  94           Initializes ISA expansion ROM.
               Shadows I/O ROM if setup request.
               Builds up free expansion ROM table.
     
  96           Initializes PCI card ROM.
               Shadows I/O ROM if setup request.
               Builds up free expansion ROM table.
               
  A0           Initialize timer counter for DOS use.
               Sets time and date.

  A4           Initializes security feature.

  AC           Enables NMI.
               Enables parity checking.
               Sets video mode.

  AE           Sets program chipset.
  
  AF           Initializes RDM (Phase III)
               Sets program chipset.

  B0           Power-on password checking.
               Displays configuration table.
               Clears memory buffer used for POST.
               Select boot device.
     
  BD           Shutdown 5.

  BE           Shutdown A.

  BF           Shutdown B.

  E0           Initializes BSP.


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Anmerkung:     Die Codes sind in alphabetischer Reihenfolge auf gefhrt,
               was nicht der Reihenfolge ihres Auftretens entspricht.
