main Project Status (11/14/2011 - 14:33:17)
Project File: ports.xise Parser Errors: No Errors
Module Name: main Implementation State: Programming File Generated
Target Device: xc3s50a-4vq100
  • Errors:
No Errors
Product Version:ISE 13.1
  • Warnings:
219 Warnings (109 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 167 1,408 11%  
Number of 4 input LUTs 62 1,408 4%  
Number of occupied Slices 132 704 18%  
    Number of Slices containing only related logic 132 132 100%  
    Number of Slices containing unrelated logic 0 132 0%  
Total Number of 4 input LUTs 62 1,408 4%  
Number of bonded IOBs 23 68 33%  
Number of BUFGMUXs 4 24 16%  
Average Fanout of Non-Clock Nets 1.72      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMo 14. Nov 14:32:32 20110217 Warnings (107 new)3 Infos (0 new)
Translation ReportCurrentMo 14. Nov 14:32:40 2011000
Map ReportCurrentMo 14. Nov 14:32:47 2011002 Infos (0 new)
Place and Route ReportCurrentMo 14. Nov 14:32:59 201102 Warnings (2 new)3 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentMo 14. Nov 14:33:03 2011005 Infos (0 new)
Bitgen ReportCurrentMo 14. Nov 14:33:10 2011000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentMo 14. Nov 14:33:11 2011
WebTalk Log FileCurrentMo 14. Nov 14:33:16 2011

Date Generated: 11/14/2011 - 14:33:17