pwm Project Status (11/11/2011 - 17:18:29)
Project File: pwm.xise Parser Errors: No Errors
Module Name: pwm Implementation State: Programming File Generated
Target Device: xc3s50a-4vq100
  • Errors:
No Errors
Product Version:ISE 13.1
  • Warnings:
209 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 310 1,408 22%  
Number of 4 input LUTs 189 1,408 13%  
Number of occupied Slices 228 704 32%  
    Number of Slices containing only related logic 228 228 100%  
    Number of Slices containing unrelated logic 0 228 0%  
Total Number of 4 input LUTs 201 1,408 14%  
    Number used as logic 189      
    Number used as a route-thru 12      
Number of bonded IOBs 23 68 33%  
Number of BUFGMUXs 4 24 16%  
Average Fanout of Non-Clock Nets 2.13      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentFr 11. Nov 17:17:44 20110207 Warnings (0 new)2 Infos (0 new)
Translation ReportCurrentFr 11. Nov 17:17:52 2011000
Map ReportCurrentFr 11. Nov 17:17:58 2011002 Infos (0 new)
Place and Route ReportCurrentFr 11. Nov 17:18:12 201102 Warnings (0 new)4 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentFr 11. Nov 17:18:16 2011005 Infos (0 new)
Bitgen ReportCurrentFr 11. Nov 17:18:23 2011000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentFr 11. Nov 17:18:23 2011
WebTalk Log FileCurrentFr 11. Nov 17:18:28 2011

Date Generated: 11/11/2011 - 17:18:29