led_blinker Project Status (06/18/2011 - 14:13:04)
Project File: blink.xise Parser Errors: No Errors
Module Name: led_blinker Implementation State: Programming File Generated
Target Device: xc3s50a-4vq100
  • Errors:
No Errors
Product Version:ISE 13.1
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 24 1,408 1%  
Number of 4 input LUTs 2 1,408 1%  
Number of occupied Slices 13 704 1%  
    Number of Slices containing only related logic 13 13 100%  
    Number of Slices containing unrelated logic 0 13 0%  
Total Number of 4 input LUTs 25 1,408 1%  
    Number used as logic 2      
    Number used as a route-thru 23      
Number of bonded IOBs 2 68 2%  
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 1.06      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentSa 18. Jun 14:10:30 2011000
Translation ReportCurrentSa 18. Jun 14:10:35 2011000
Map ReportCurrentSa 18. Jun 14:10:39 2011002 Infos (0 new)
Place and Route ReportCurrentSa 18. Jun 14:12:51 2011004 Infos (1 new)
Power Report     
Post-PAR Static Timing ReportCurrentSa 18. Jun 14:12:54 2011005 Infos (0 new)
Bitgen ReportCurrentSa 18. Jun 14:12:59 2011000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentSa 18. Jun 14:12:59 2011
WebTalk Log FileCurrentSa 18. Jun 14:13:04 2011

Date Generated: 06/18/2011 - 14:13:04