| Project Statistics |
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PROP_FitterReportFormat=HTML |
| PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
| PROP_ManualCompileOrderImp=false |
PROP_OverwriteSym=true |
| PROP_ProjectDescription=for UNIC XC3S50A |
PROP_PropSpecInProjFile=Store all values |
| PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthTopFile=changed |
| PROP_Top_Level_Module_Type=Schematic |
PROP_UseSmartGuide=false |
| PROP_UserConstraintEditorPreference=Text Editor |
PROP_intProjectCreationTimestamp=2011-06-18T17:47:43 |
| PROP_intWbtProjectID=3BAEA88D779D49C282807B482362B3EE |
PROP_intWbtProjectIteration=18 |
| PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
| PROP_AutoTop=true |
PROP_DevFamily=Spartan3A and Spartan3AN |
| PROP_DevDevice=xc3s50a |
PROP_DevFamilyPMName=spartan3a |
| PROP_DevPackage=vq100 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
| PROP_DevSpeed=-4 |
PROP_PreferredLanguage=VHDL |
| FILE_SCHEMATIC=1 |
FILE_UCF=1 |
| FILE_VHDL=2 |