Device Usage Statistics Report

Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.

Software Version and Target Device
Product Version:	ISE:13.1 (WebPack) - O.40d	Target Family:	Spartan3A and Spartan3AN
OS Platform:	NT64	Target Device:	xc3s50a
Project ID (random number)	458aafca6a694c07afdd1d8c3e594796.3BAEA88D779D49C282807B482362B3EE.18	Target Package:	vq100
Registration ID	174235926_0_0_051	Target Speed:	-4
Date Generated	2011-11-11T17:18:23	Tool Flow	ISE

User Environment
OS Name	Microsoft Windows 7 , 64-bit	OS Release	Service Pack 1 (build 7601)
CPU Name	AMD Phenom(tm) 8750 Triple-Core Processor	CPU Speed	2400 MHz
CPU Name	AMD Phenom(tm) 8750 Triple-Core Processor	CPU Speed	2400 MHz

Device Usage Statistics
Macro Statistics	Miscellaneous Statistics	Net Statistics	Site Usage
Adders/Subtractors=1 32-bit subtractor=1 Comparators=3 4-bit comparator equal=1 4-bit comparator not equal=1 8-bit comparator less=1 Counters=2 12-bit up counter=1 32-bit down counter=1 Multiplexers=1 32-bit 8-to-1 multiplexer=1 Registers=459 Flip-Flops=459	MiscellaneousStatistics AGG_BONDED_IO=23 AGG_IO=23 AGG_SLICE=228 NUM_4_INPUT_LUT=201 NUM_BONDED_IBUF=5 NUM_BONDED_IOB=18 NUM_BUFGMUX=4 NUM_CYMUX=97 NUM_LUT_RT=12 NUM_SLICEL=228 NUM_SLICE_FF=310 NUM_XOR=76	NetStatistics NumNets_Active=471 NumNets_Gnd=1 NumNets_Vcc=1 NumNodesOfType_Active_CLKPIN=175 NumNodesOfType_Active_CNTRLPIN=143 NumNodesOfType_Active_DOUBLE=747 NumNodesOfType_Active_DUMMY=508 NumNodesOfType_Active_DUMMYESC=5 NumNodesOfType_Active_GLOBAL=55 NumNodesOfType_Active_HFULLHEX=10 NumNodesOfType_Active_HUNIHEX=36 NumNodesOfType_Active_INPUT=792 NumNodesOfType_Active_IOBOUTPUT=5 NumNodesOfType_Active_OMUX=500 NumNodesOfType_Active_OUTPUT=446 NumNodesOfType_Active_PREBXBY=381 NumNodesOfType_Active_VFULLHEX=12 NumNodesOfType_Active_VLONG=5 NumNodesOfType_Active_VUNIHEX=12 NumNodesOfType_Gnd_DOUBLE=7 NumNodesOfType_Gnd_INPUT=17 NumNodesOfType_Gnd_OMUX=9 NumNodesOfType_Gnd_OUTPUT=7 NumNodesOfType_Gnd_PREBXBY=2 SiteStatistics IBUF-DIFFMTB=2 IBUF-DIFFSTB=3 IOB-DIFFMLR=3 IOB-DIFFMTB=6 IOB-DIFFSLR=2 IOB-DIFFSTB=7 SLICEL-SLICEM=102	SiteSummary BUFGMUX=4 BUFGMUX_GCLKMUX=4 BUFGMUX_GCLK_BUFFER=4 IBUF=5 IBUF_DELAY_ADJ_BBOX=5 IBUF_INBUF=5 IBUF_PAD=5 IOB=18 IOB_OUTBUF=18 IOB_PAD=18 SLICEL=228 SLICEL_C1VDD=32 SLICEL_C2VDD=30 SLICEL_CYMUXF=50 SLICEL_CYMUXG=47 SLICEL_F=101 SLICEL_F5MUX=1 SLICEL_FFX=160 SLICEL_FFY=150 SLICEL_G=100 SLICEL_GNDF=14 SLICEL_GNDG=13 SLICEL_XORF=38 SLICEL_XORG=38

Configuration Data
BUFGMUX S=[S_INV:4] [S:0] BUFGMUX_GCLKMUX DISABLE_ATTR=[LOW:4] S=[S_INV:4] [S:0] IBUF_DELAY_ADJ_BBOX DELAY_ADJ_ATTRBOX=[FIXED:5] IBUF_DELAY_VALUE=[DLY0:5] IFD_DELAY_VALUE=[DLY0:5] SEL_IN=[SEL_IN:5] [SEL_IN_INV:0] IBUF_PAD IOATTRBOX=[LVCMOS33:5] IOB O1=[O1_INV:0] [O1:18] T1=[T1_INV:0] [T1:1] IOB_OUTBUF IN=[IN_INV:0] [IN:18] SUSPEND=[3STATE:18] TRI=[TRI_INV:0] [TRI:1]	IOB_PAD DRIVEATTRBOX=[12:18] IOATTRBOX=[LVCMOS33:18] SLEW=[SLOW:18] SLICEL BX=[BX_INV:1] [BX:119] BY=[BY:126] [BY_INV:0] CE=[CE:83] [CE_INV:24] CIN=[CIN_INV:0] [CIN:44] CLK=[CLK:175] [CLK_INV:0] SR=[SR:34] [SR_INV:1] SLICEL_CYMUXF 0=[0:50] [0_INV:0] 1=[1_INV:1] [1:49]	SLICEL_CYMUXG 0=[0:47] [0_INV:0] SLICEL_F5MUX S0=[S0:1] [S0_INV:0] SLICEL_FFX CE=[CE:81] [CE_INV:24] CK=[CK:160] [CK_INV:0] D=[D:160] [D_INV:0] FFX_INIT_ATTR=[INIT0:160] FFX_SR_ATTR=[SRLOW:160] LATCH_OR_FF=[FF:160] REV=[REV_INV:0] [REV:25] SR=[SR:25] [SR_INV:0] SYNC_ATTR=[ASYNC:160]	SLICEL_FFY CE=[CE:83] [CE_INV:24] CK=[CK:150] [CK_INV:0] D=[D:150] [D_INV:0] FFY_INIT_ATTR=[INIT0:150] FFY_SR_ATTR=[SRLOW:150] LATCH_OR_FF=[FF:150] SR=[SR:9] [SR_INV:1] SYNC_ATTR=[ASYNC:147] [SYNC:3] SLICEL_XORF 1=[1_INV:1] [1:37]

Pin Data
BUFGMUX I0=4 O=4 S=4 BUFGMUX_GCLKMUX I0=4 OUT=4 S=4 BUFGMUX_GCLK_BUFFER IN=4 OUT=4 IBUF I=5 PAD=5 IBUF_DELAY_ADJ_BBOX IBUF_OUT=5 SEL_IN=5 IBUF_INBUF IN=5 OUT=5 IBUF_PAD PAD=5 IOB O1=18 PAD=18 T1=1 IOB_OUTBUF IN=18 OUT=18 TRI=1	IOB_PAD PAD=18 SLICEL BX=120 BY=126 CE=107 CIN=44 CLK=175 COUT=47 F1=101 F2=79 F3=55 F4=20 G1=99 G2=77 G3=54 G4=17 SR=35 X=43 XQ=160 Y=39 YQ=150 SLICEL_C1VDD 1=32	SLICEL_C2VDD 1=30 SLICEL_CYMUXF 0=50 1=50 OUT=50 S0=50 SLICEL_CYMUXG 0=47 1=47 OUT=47 S0=47 SLICEL_F A1=101 A2=79 A3=55 A4=20 D=101 SLICEL_F5MUX F=1 G=1 OUT=1 S0=1 SLICEL_FFX CE=105 CK=160 D=160 Q=160 REV=25 SR=25	SLICEL_FFY CE=107 CK=150 D=150 Q=150 SR=10 SLICEL_G A1=99 A2=77 A3=54 A4=17 D=100 SLICEL_GNDF 0=14 SLICEL_GNDG 0=13 SLICEL_XORF 0=38 1=38 O=38 SLICEL_XORG 0=38 1=38 O=38

Tool Usage

Command Line History

xst -intstyle ise -ifn <ise_file>
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s50a-vq100-4 <fname>.ngc <fname>.ngd
map -intstyle ise -p xc3s50a-vq100-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
sch2hdl -intstyle ise -family spartan3a -flat -suppress -vhdl <fname>.vhf -w <fname>.sch
ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc <fname>.ucf -p xc3s50a-vq100-4 <fname>.ngc <fname>.ngd
map -intstyle ise -p xc3s50a-vq100-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
bitgen -intstyle ise -f <fname>.ut <fname>.ncd
xst -intstyle ise -ifn <ise_file>
ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc <fname>.ucf -p xc3s50a-vq100-4 <fname>.ngc <fname>.ngd
map -intstyle ise -p xc3s50a-vq100-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
bitgen -intstyle ise -f <fname>.ut <fname>.ncd
xst -intstyle ise -ifn <ise_file>
ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc <fname>.ucf -p xc3s50a-vq100-4 <fname>.ngc <fname>.ngd
map -intstyle ise -p xc3s50a-vq100-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
bitgen -intstyle ise -f <fname>.ut <fname>.ncd
xst -intstyle ise -ifn <ise_file>
ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc <fname>.ucf -p xc3s50a-vq100-4 <fname>.ngc <fname>.ngd
map -intstyle ise -p xc3s50a-vq100-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
bitgen -intstyle ise -f <fname>.ut <fname>.ncd

Software Quality
Run Statistics
_impact	10	9	0	0	0	0	0
bitgen	57	57	0	0	0	0	0
edif2ngd	8	8	0	0	0	0	0
map	68	64	0	0	0	0	0
netgen	8	8	0	0	0	0	0
ngcbuild	11	11	0	0	0	0	0
ngdbuild	74	74	0	0	0	0	0
obngc	8	8	0	0	0	0	0
par	64	59	2	0	0	0	0
trce	59	59	0	0	0	0	0
xst	246	246	0	0	0	0	0

Help Statistics
Help files
/doc/usenglish/isehelp/ise_c_using_xst_for_synthesis.htm ( 1 )	/doc/usenglish/isehelp/sse_c_attr_traits.htm ( 1 )
/doc/usenglish/isehelp/sse_c_considerations.htm ( 1 )	/doc/usenglish/isehelp/sse_c_files.htm ( 1 )
/doc/usenglish/isehelp/sse_c_intro_to_attrs.htm ( 2 )	/doc/usenglish/isehelp/sse_c_iomarkers.htm ( 1 )
/doc/usenglish/isehelp/sse_c_nets.htm ( 1 )	/doc/usenglish/isehelp/sse_c_overview.htm ( 2 )
/doc/usenglish/isehelp/sse_c_symbols.htm ( 2 )	/doc/usenglish/isehelp/sse_p_adding_attr.htm ( 1 )
/doc/usenglish/isehelp/sse_p_displaying_attr_sch_net.htm ( 1 )

Project Statistics
PROP_Enable_Message_Filtering=false	PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced	PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false	PROP_OverwriteSym=true
PROP_ProjectDescription=Frequenz- und PWM-Generator	PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog)	PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=Schematic	PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor	PROP_intProjectCreationTimestamp=2011-06-18T17:47:43
PROP_intWbtProjectID=3BAEA88D779D49C282807B482362B3EE	PROP_intWbtProjectIteration=18
PROP_intWorkingDirLocWRTProjDir=Same	PROP_intWorkingDirUsed=No
PROP_xilxNgdbld_AUL=true	PROP_AutoTop=true
PROP_DevFamily=Spartan3A and Spartan3AN	PROP_DevDevice=xc3s50a
PROP_DevFamilyPMName=spartan3a	PROP_DevPackage=vq100
PROP_Synthesis_Tool=XST (VHDL/Verilog)	PROP_DevSpeed=-4
PROP_PreferredLanguage=VHDL	FILE_SCHEMATIC=1
FILE_UCF=1	FILE_VHDL=3

Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUF=33	NGDBUILD_NUM_BUFG=3	NGDBUILD_NUM_BUFGP=1	NGDBUILD_NUM_FD=63
NGDBUILD_NUM_FDCP=32	NGDBUILD_NUM_FDE=212	NGDBUILD_NUM_FDR=3	NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUF=3	NGDBUILD_NUM_IBUFG=1	NGDBUILD_NUM_INV=36	NGDBUILD_NUM_LUT1=12
NGDBUILD_NUM_LUT2=47	NGDBUILD_NUM_LUT3=72	NGDBUILD_NUM_LUT4=37	NGDBUILD_NUM_MUXCY=97
NGDBUILD_NUM_MUXF5=1	NGDBUILD_NUM_OBUF=17	NGDBUILD_NUM_OBUFT=1	NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=76
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUF=33	NGDBUILD_NUM_BUFG=4	NGDBUILD_NUM_FD=63	NGDBUILD_NUM_FDCP=32
NGDBUILD_NUM_FDE=212	NGDBUILD_NUM_FDR=3	NGDBUILD_NUM_GND=1	NGDBUILD_NUM_IBUF=3
NGDBUILD_NUM_IBUFG=2	NGDBUILD_NUM_INV=36	NGDBUILD_NUM_LUT1=12	NGDBUILD_NUM_LUT2=47
NGDBUILD_NUM_LUT3=72	NGDBUILD_NUM_LUT4=37	NGDBUILD_NUM_MUXCY=97	NGDBUILD_NUM_MUXF5=1
NGDBUILD_NUM_OBUF=17	NGDBUILD_NUM_OBUFT=1	NGDBUILD_NUM_VCC=1	NGDBUILD_NUM_XORCY=76