led_pb Project Status (02/14/2014 - 15:04:59)
Project File: | led_pb.xise | Parser Errors: | No Errors
Module Name: | led_pb | Implementation State: | Programming File Generated
Target Device: | xc6slx16-3csg324 | Errors: | No Errors
Product Version: | ISE 14.7 | Warnings: | No Warnings
Design Goal: | Balanced | Routing Results: | All Signals Completely Routed
Design Strategy: | Xilinx Default (unlocked) | Timing Constraints: |
Environment: | System Settings | Final Timing Score: | 0 (Timing Report)

Device Utilization Summary | [-]
Slice Logic Utilization | Used | Available | Utilization | Note(s)
Number of Slice Registers | 0 | 18,224 | 0% |
Number of Slice LUTs | 1 | 9,112 | 1% |
Number used as logic | 1 | 9,112 | 1% |
Number using O6 output only | 1 |  |  |
Number using O5 output only | 0 |  |  |
Number using O5 and O6 | 0 |  |  |
Number used as ROM | 0 |  |  |
Number used as Memory | 0 | 2,176 | 0% |
Number of occupied Slices | 1 | 2,278 | 1% |
Number of MUXCYs used | 0 | 4,556 | 0% |
Number of LUT Flip Flop pairs used | 1 |  |  |
Number with an unused Flip Flop | 1 | 1 | 100% |
Number with an unused LUT | 0 | 1 | 0% |
Number of fully used LUT-FF pairs | 0 | 1 | 0% |
Number of slice register sites lost to control set restrictions | 0 | 18,224 | 0% |
Number of bonded IOBs | 3 | 232 | 1% |
Number of LOCed IOBs | 3 | 3 | 100% |
Number of RAMB16BWERs | 0 | 32 | 0% |
Number of RAMB8BWERs | 0 | 64 | 0% |
Number of BUFIO2/BUFIO2_2CLKs | 0 | 32 | 0% |
Number of BUFIO2FB/BUFIO2FB_2CLKs | 0 | 32 | 0% |
Number of BUFG/BUFGMUXs | 0 | 16 | 0% |
Number of DCM/DCM_CLKGENs | 0 | 4 | 0% |
Number of ILOGIC2/ISERDES2s | 0 | 248 | 0% |
Number of IODELAY2/IODRP2/IODRP2_MCBs | 0 | 248 | 0% |
Number of OLOGIC2/OSERDES2s | 0 | 248 | 0% |
Number of BSCANs | 0 | 4 | 0% |
Number of BUFHs | 0 | 128 | 0% |
Number of BUFPLLs | 0 | 8 | 0% |
Number of BUFPLL_MCBs | 0 | 4 | 0% |
Number of DSP48A1s | 0 | 32 | 0% |
Number of ICAPs | 0 | 1 | 0% |
Number of MCBs | 0 | 2 | 0% |
Number of PCILOGICSEs | 0 | 2 | 0% |
Number of PLL_ADVs | 0 | 2 | 0% |
Number of PMVs | 0 | 1 | 0% |
Number of STARTUPs | 0 | 1 | 0% |
Number of SUSPEND_SYNCs | 0 | 1 | 0% |
Average Fanout of Non-Clock Nets | 1.50 |  |  |

Performance Summary | [-]
Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report
Timing Constraints: |  |  |

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | Fr 14. Feb 15:04:27 2014 | 0 | 0 | 0
Translation Report | Current | Fr 14. Feb 15:04:34 2014 | 0 | 0 | 0
Map Report | Current | Fr 14. Feb 15:04:45 2014 | 0 | 0 | 6 Infos (6 new)
Place and Route Report | Current | Fr 14. Feb 15:04:52 2014 | 0 | 0 | 2 Infos (2 new)
Power Report |  |  |  |  |
Post-PAR Static Timing Report | Current | Fr 14. Feb 15:04:57 2014 | 0 | 0 | 4 Infos (4 new)
Bitgen Report | Current | Fr 14. Feb 15:06:34 2014 | 0 | 0 | 0

Secondary Reports | [-]
Report Name | Status | Generated
WebTalk Report | Current | Fr 14. Feb 15:11:02 2014
WebTalk Log File | Current | Fr 14. Feb 15:11:23 2014

Date Generated: 02/14/2014 - 15:12:37