Cx86.exe
--------

Dieses Programm kontrolliert Features der Cyrix 6x86-Prozessoren.
Es stammt von Grzegorz Mazur (http://grafi.ii.pw.edu.pl/gbm/x86). Zu
beachten sind die Bestimmungen im folgenden Original-Readme.



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 Basic information on Cx86!

 Cx CPU performance control tool version 1.20
 supports 5x86, 6x86 (user-friendly way)
 and all 486-class (hacker-friendly way) CPUs

 **** Temporary version ****
 This version may contain many bugs. Please report them to the
 Author (contact shown below).

 Usage:
 ------

 Setting feature bits:
 To set a feature type <name>, to reset type ~<name> in command line.
 Feature names are described below, they can also be viewed using
 option "-show".

 Setting special features of Cx8x86:
 use options -ploopen, -ploopdis, -farjumps - described below

 Setting any bits or control registers:
 You must have Cyrix Data Book to know their addresses. To access
 registers "manually", enter -debug option on command line and play.
 Note that you can also set these bits/registers in autoexec.bat -
 to do so, invoke cx! -debug <inputfile, preparing the response file
 for cx! debug mode.
 I realize that this description is too short, but 1.it is for hackers
 2. longer one will follow soon

 Options:
  -safe  set safe features (= rstk_en ~lsser mem_byp dte_en)
  -show  show feature bits
  -dump  dump all Cyrix configuration registers
  -debug enter debug mode (no description yet, but you can enter
		question mark while in debug mode...)
  -ploopen slow down LOOP instruction (needed for compatibility with
           some timing-dependent software
  -ploopdis reverse the effect of -ploopen
  -farjumps enable far jump hits in Branch Target Buffer

 ----------------------------------------------------------------
 Disclaimer

 I do not guarantee anything regarding this program...
 Use at your own risk.
 You have been warned...

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 Licence information

 The tool is shareware outside of Poland.

 Polish users should contact Infotex sc for licensing info
 -> ul. Gwiazdzista 50a, 01-651 Warszawa, tel. (22)333050.

 Foreign users:
 The shareware trial period is 30 days. After this period expires
 you are obliged to pay the registration fee or to stop using the
 program. Please contact the author to register. Registered users
 will be notified about new versions. The registration fee is $14.

 Current version is available from http URL given below.
 
 Grzegorz Mazur <gbm@ii.pw.edu.pl>,
 http://grafi.ii.pw.edu.pl/gbm/x86

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 ----------------------------------------------------------------
 Cx5x86 Performance Features
 
 Copyright 1996 by Grzegorz Mazur,
 mailto:gbm@ii.pw.edu.pl
 http://grafi.ii.pw.edu.pl/gbm
 
 All the names used in this text are the property of their owners.
 
 This text accompanies Cx86! - Cx5x86/6x86 control utility.
 The current version of Cx86! is available from
 http://grafi.ii.pw.edu.pl/gbm/x86
 ----------------------------------------------------------------
 
 Some Background
 
 Cx5x86 is a superpipelined CPU. This means that its pipeline is
 longer than that of "typical" CPU - it contains 6 stages
 (classic 486s are 5-stage). The superpipeline can achieve higher
 execution speed that simple pipeline, but it is also more
 sensitive to various execution delays resulting from branching
 and memory operations. To enhance the performance of
 a superpipeline (to make it reasonably faster than simple
 pipeline) several mechanisms must be employed. Some of them are
 heuristic, some deterministic. These mechanisms can cause
 differences in CPU's behavior when compared to simple pipelined
 implementations. And we all know how sensitive (= ill behaved)
 is the software written for PCs. So we need a tool to control
 the advanced features of Cx5x86. Such tool has two purposes:
 to make the CPU run faster and to make it run safer when
 necessary. Below you can find the description of performance
 features controlled by Cx5x86!, the Cx5x86 performance control
 tool.
 
 Cx5x86 is capable of setting bits in Cx5x86 CPU control
 registers. These bits control functions of speedup mechanisms
 built into the CPU. The following bits can be controlled by
 the program:
 
 BTB_EN Branch Target Buffer ENable
 The Branch Target Buffer is a hardware structure inside the CPU
 that speeds up the execution of static (fixed-destination)
 branch instructions (conditional branches and "normal"
 unconditional branches, including subroutine calls. The BTB
 records the address of branch instruction, its target address
 and execution history (taken / not taken) for conditional
 branches. Certainly the CPU works faster with BTB ENABLED.
 
 RSTK_EN Return STacK ENable
 The internal, hardware Return Stack inside the CPU records
 the return addresses pushed onto software stack by subroutine
 call instructions. The return instructions can be significantly
 accelerated by taking the addresses from this small hardware
 stack instead of taking them from memory. The CPU works faster
 with Return Stack ENABLED.
 
 LOOP_EN Loop Enable
 The 5x86 contains 48-bytes long Instruction Prefetch Buffer.
 Normally the buffer is flushed during the execution of branch
 instruction. By activating the feature we can force the CPU
 not to flush the buffer during branch if its target resides
 in the buffer. This significantly accelerates short loops.
 The CPU works faster with Loop Buffer enabled.
 
 AIS All Instructions stalled Serialize
 The description is as advanced as the feature itself. If
 enabled, it causes the cpu to serialize all pending memory
 operations whenever the instruction is stalled in the
 pipeline. The CPU works faster when AIS is DISABLED.
 
 MLR Misaligned Loads Reordering
 Another advanced option. The CPU can reorder memory read
 operations to perform them faster. The CPU works faster
 with MLR ENABLED.
 
 LSSER Load and Store SERialize
 The pipeline can work a lot faster if it is not obliged to
 perform memory operations in strict order. Note that memory
 reads are performed in early stages, and memory writes in
 terminal stages. So if we containing memory write followed
 by memory read (with different memory locations), the CPU
 will perform read operation before write. Certainly the CPU
 properly handles consecutive references to the same memory
 location. The CPU works faster with serialization DISABLED.
 The setting of this option does not influence operation of
 memory devices in physical address range 640 KB .. 1 MB
 - the references to these addresses are always serialized.
 
 BWRT Burst Write
 Setting this feature allows the CPU to perform memory writes
 using burst transfers. Practically this refers to transfering
 data between CPU cache and secondary cache. Reads are performed
 using burst mode always whenever it makes sense. The burst
 transfer can be up to 37.5% faster than single word transfer,
 so the CPU works faster with Burst Write enabled.
 
 LINBRST LINear BuRST
 Intel CPUs perform burst operation in strange manner:
 the address sequence is not quite obvious and sometimes they
 prepend extra cycle before the burst. By default the Cx5x86
 mimics this behavior. If the motherboard can handle Linerar
 Burst mode, the system wil work faster with LIBRST enabled.
 
 MEM_BYP MEMory read data BYPassing
 Setting this bit enables bypass path from memory read stage.
 This way data read from memory is forwarded to use by
 successive instructions before it is written to registers.
 
 DTE_EN page Directory Table Entry cache Enable
 Setting this bit causes the CPU to cache descriptors from Page
 Directory Table in a small buffer. This will slightly speed up
 the Paging Unit.
 
 FP_FAST FAST reporting of Floating Point exceptions
 If we don't need to strictly follow IEEE 754 guidelines and
 have no interest in precise handling of FPU exceptions (which
 is true if we are not involved in nuclear physics or spacecraft
 design), we can disable the feature. This will cause the FPU to
 work faster.
 
 SMCC Self-Modifying Code Checking Enable
 Well behaved programs never modify their code. PC programs,
 especially those written by hackers use to modify their code.
 This makes the CPUs life harder. If don't use hackers' code,
 we can disable the feature to make our CPU run faster.
 
 End of description.

